ST STM32L4 5 Series Reference Manual page 250

Reset and clock control (RCC)
Bit 31 LPTIM1EN: Low power timer 1 clock enable
Bit 30 OPAMPEN: OPAMP interface clock enable
Bit 29 DAC1EN: DAC1 interface clock enable
Bit 28 PWREN: Power interface clock enable
Bit 27 Reserved, must be kept at reset value.
Bit 26 CAN2EN: CAN2 clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices)
0: CAN2 clock disabled
1: CAN2 clock enabled
Bit 25 CAN1EN: CAN1 clock enable
Bit 24 CRSEN: Clock Recovery System clock enable (This bit is reserved for
STM32L475xx/476xx/486xx devices)
0: CRS clock disabled
1: CRS clock enabled
Bit 23 I2C3EN: I2C3 clock enable
Bit 22 I2C2EN: I2C2 clock enable
Bit 21 I2C1EN: I2C1 clock enable
Bit 20 UART5EN: UART5 clock enable
250/1830
Set and cleared by software.
0: LPTIM1 clock disabled
1: LPTIM1 clock enabled
Set and cleared by software.
0: OPAMP interface clock disabled
1: OPAMP interface clock enabled
Set and cleared by software.
0: DAC1 interface clock disabled
1: DAC1 interface clock enabled
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Set and cleared by software
Set and cleared by software.
0: CAN1 clock disabled
1: CAN1 clock enabled
Set and cleared by software
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Set and cleared by software.
0: UART5 clock disabled
1: UART5 clock enabled
DocID024597 Rev 5
RM0351