Otg Low-Power Modes; Table 222. Compatibility Of Stm32 Low Power Modes With The Otg - ST STM32F446 Series Reference Manual

RM0390
The end of periodic frame interrupt (OTG_GINTSTS/EOPF) is used to notify the application
when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic
frame interval field in the device configuration register (PFIVL bit in OTG_DCFG). This
feature can be used to determine if all of the isochronous traffic for that frame is complete.
31.9

OTG low-power modes

Table 222

Table 222. Compatibility of STM32 low power modes with the OTG

Mode
Run MCU fully active
USB suspend exit causes the device to exit Sleep mode. Peripheral
Sleep
registers content is kept.
USB suspend exit causes the device to exit Stop mode. Peripheral
Stop
registers content is kept
Powered-down. The peripheral must be reinitialized after exiting
Standby
Standby mode.
1. Within Stop mode there are different possible settings. Some restrictions may also exist, please refer to
controller (PWR) to understand which (if any) restrictions apply when using OTG.
The following bits and procedures reduce power consumption.
The power consumption of the OTG PHY is controlled by two or three bits in the general
core configuration register, depending on OTG revision supported.
• PHY power down (OTG_GCCFG/PWRDWN)
It switches on/off the full-speed transceiver module of the PHY. It must be preliminarily
set to allow any USB operation
•
V
BUS
It switches on/off the V
Power reduction techniques are available while in the USB suspended state, when the USB
session is not yet valid or the device is disconnected.
•
Stop PHY clock (STPPCLK bit in OTG_PCGCCTL)
When setting the stop PHY clock bit in the clock gating control register, most of the
48 MHz clock domain internal to the OTG full-speed core is switched off by clock
gating. The dynamic power consumption due to the USB clock switching activity is cut
even if the 48 MHz clock input is kept running by the application
Most of the transceiver is also disabled, and only the part in charge of detecting the
asynchronous resume or remote wakeup event is kept alive.
•
Gate HCLK (GATEHCLK bit in OTG_PCGCCTL)
When setting the Gate HCLK bit in the clock gating control register, most of the system
clock domain internal to the OTG_FS/OTG_HS core is switched off by clock gating.
Only the register read and write interface is kept alive. The dynamic power
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
below defines the STM32 low power modes and their compatibility with the OTG.
Description
(1)
.
detection enable (OTG_GCCFG/VBDEN)
BUS
sensing comparators associated with OTG operations
RM0390 Rev 4
USB compatibility
Required when USB not in
suspend state.
Available while USB is in
suspend state.
Available while USB is in
suspend state.
Not compatible with USB
applications.
Section 5: Power
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