ST STM32F446 Series Reference Manual page 1120

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Bit 15 PHYLPC: PHY Low-power clock select for USB OTG HS
This bit selects either 480 MHz or 48 MHz (low-power) PHY mode. In FS and LS modes, the
PHY can usually operate on a 48 MHz clock to save power.
0: 480 MHz internal PLL clock
1: 48 MHz external clock
In 480 MHz mode, the UTMI interface operates at either 60 or 30 MHz, depending on
whether the 8- or 16-bit data width is selected. In 48 MHz mode, the UTMI interface operates
at 48 MHz in FS and LS modes.
Bit 14 Reserved, must be kept at reset value.
Bits 13:10 TRDT[3:0]: USB turnaround time
These bits allows to set the turnaround time in PHY clocks. They must be configured
according to
the application AHB frequency. Higher TRDT values allow stretching the USB response time
to IN tokens in order to compensate for longer AHB read access latency to the data FIFO.
Note: Only accessible in device mode.
Bit 9 HNPCAP: HNP-capable
The application uses this bit to control the OTG_FS/OTG_HS controller's HNP capabilities.
0: HNP capability is not enabled.
1: HNP capability is enabled.
Note: Accessible in both device and host modes.
Bit 8 SRPCAP: SRP-capable
The application uses this bit to control the OTG_FS/OTG_HS controller's SRP capabilities. If
the core operates as a non-SRP-capable
B-device, it cannot request the connected A-device (host) to activate V
session.
0: SRP capability is not enabled.
1: SRP capability is enabled.
Note: Accessible in both device and host modes.
Bit 7 Reserved, must be kept at reset value.
Bit 6 PHYSEL: Full Speed serial transceiver select for USB OTG FS
This bit is always 1 with read-only access.
Bit 6 PHYSEL: Full speed serial transceiver select for USB OTG HS
0: USB 2.0 external ULPI high-speed PHY.
1: USB 1.1 full-speed serial transceiver.
Bit 5 Reserved, must be kept at reset value.
Bit 4 Reserved, must be kept at reset value.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 TOCAL[2:0]: FS timeout calibration
The number of PHY clocks that the application programs in this field is added to the full-
speed interpacket timeout duration in the core to account for any additional delays
introduced by the PHY. This can be required, because the delay introduced by the PHY in
generating the line state condition can vary from one PHY to another.
The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of enumeration. The number of bit
times added per PHY clock is 0.25 bit times.
1120/1328
Table 228: TRDT values (FS)
RM0390 Rev 4
or Table 229: TRDT values
RM0390
(HS), depending on
and start a
BUS