Secure digital input/output interface (SDIO)
47
46
[45:40]
[39:8] Argument
field
[7:1]
0
The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card. In this case,
the 16 bits of response are the SD I/O-only values:
•
Bit [15] COM_CRC_ERROR
•
Bit [14] ILLEGAL_COMMAND
•
Bit [13] ERROR
•
Bits [12:0] Reserved
29.6
SDIO I/O card-specific operations
The following features are SD I/O-specific operations:
•
SDIO read wait operation by SDIO_D2 signalling
•
SDIO read wait operation by stopping the clock
•
SDIO suspend/resume operation (write and read suspend)
•
SDIO interrupts
The SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read
suspend that does not need specific hardware implementation.
29.6.1
SDIO I/O read wait operation by SDIO_D2 signalling
It is possible to start the readwait interval before the first block is received: when the data
path is enabled (SDIO_DCTRL[0] bit set), the SDIO-specific operation is enabled
(SDIO_DCTRL[11] bit set), read wait starts (SDIO_DCTRL[10] =0 and SDIO_DCTRL[8] =1)
and data direction is from card to SDIO (SDIO_DCTRL[1] = 1), the DPSM directly moves
from Idle to Readwait. In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock
cycles. In this state, when you set the RWSTOP bit (SDIO_DCTRL[9]), the DPSM remains
in Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle (in
accordance with SDIO specification). The DPSM then starts waiting again until it receives
data from the card. The DPSM will not start a readwait interval while receiving a block even
if read wait start is set: the readwait interval will start after the CRC is received. The
RWSTOP bit has to be cleared to start a new read wait operation. During the readwait
interval, the SDIO can detect SDIO interrupts on SDIO_D1.
1014/1328
Bit position
Width (bits)
1
1
6
[31:16]
16
[15:0]
16
7
1
Table 210. R6 response
Value
0
Start bit
0
Transmission bit
'101000'
CMD40
X
RCA [31:16] of winning card or of the host
X
Not defined. May be used for IRQ data
X
CRC7
1
End bit
RM0390 Rev 4
RM0390
Description
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