Table 226. Data Fifo (Dfifo) Access Register Map - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Table 225. Device-mode control and status registers (continued)
Acronym
OTG_DOEPINTx
OTG_DOEPTSIZ0
OTG_DOEPDMAx
OTG_DOEPCTLx
OTG_DOEPCTLx
OTG_DOEPTSIZx
OTG_DOEPTSIZx
Data FIFO (DFIFO) access register map
These registers, available in both host and device modes, are used to read or write the FIFO
space for a specific endpoint or a channel, in a given direction. If a host channel is of type
IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the
FIFO can only be written on the channel.
Device IN endpoint 0/Host OUT Channel 0: DFIFO write access
Device OUT endpoint 0/Host IN Channel 0: DFIFO read access
Device IN endpoint 1/Host OUT Channel 1: DFIFO write access
Device OUT endpoint 1/Host IN Channel 1: DFIFO read access
1110/1328
Offset
address
0xB08
Section 31.15.55: OTG device OUT endpoint x interrupt register
0XB28
(OTG_DOEPINTx) (x = 0..5[FS] /8[HS], where x = Endpoint number)
...
for USB_OTG HS
0xC08
Section 31.15.56: OTG device OUT endpoint 0 transfer size register
0xB10
(OTG_DOEPTSIZ0)
0xB14
0xB34
Section 31.15.57: OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) (x = 0..8, where x = endpoint number)
...
0xC14
0xB20
Section 31.15.58: OTG device OUT endpoint x control register
0xB40
(OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number)
...
for USB_OTG FS
0xBA0
0xB20
Section 31.15.58: OTG device OUT endpoint x control register
0xB40
(OTG_DOEPCTLx) (x = 1..5[FS] /8[HS], where x = endpoint number)
...
for USB_OTG HS
0xC00
0xB30
Section 31.15.59: OTG device OUT endpoint x transfer size register
0xB50
(OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number)
...
for USB_OTG FS
0xBB0
0xB30
Section 31.15.59: OTG device OUT endpoint x transfer size register
0xB50
(OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS], where x = Endpoint number)
..
for USB_OTG HS
0xBF0

Table 226. Data FIFO (DFIFO) access register map

FIFO access register section
RM0390 Rev 4
Register name
Offset address
0x1000–0x1FFC
0x2000–0x2FFC
RM0390
Access
w
r
w
r