Otg Interrupt Mask Register (Otg_Gintmsk) - ST STM32F446 Series Reference Manual

RM0390
31.15.7

OTG interrupt mask register (OTG_GINTMSK)

Address offset: 0x018
Reset value: 0x0000 0000
This register works with the core interrupt register to interrupt the application. When an
interrupt bit is masked, the interrupt associated with that bit is not generated. However, the
core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
31 30 29
DISCIN CIDSC
WUIM SRQIM
T HGM
rw rw rw
15 14 13
EOPF ISOOD ENUM USBRS
M RPM DNEM
rw rw rw
Note: Configuration register for USB OTG FS
31 30 29
DISCIN CIDSC
WUIM SRQIM
T HGM
rw rw rw
15 14 13
EOPF ISOOD ENUM USBRS
M RPM DNEM
rw rw rw
Note: Configuration register for USB OTG HS
Bit 31 WUIM: Resume/remote wakeup detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 30 SRQIM: Session request/new session detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
Bit 29 DISCINT: Disconnect detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.
Bit 28 CIDSCHGM: Connector ID status change mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and device modes.
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
28 27 26 25
LPMIN PTXFE
HCIM
TM M
rw rw rw rw
12 11 10 9
USBSU ESUSP
Res.
T SPM M
rw rw rw
28 27 26 25
LPMIN PTXFE
HCIM
TM M
rw rw rw rw
12 11 10 9
USBSU ESUSP
Res.
T SPM M
rw rw rw
24 23 22
IPXFR
RSTDE M/IISO
PRTIM Res.
TM OXFR
rw rw
8 7 6
GONA GINAK NPTXF
Res.
KEFFM EFFM
rw rw
24 23 22
IPXFR
RSTDE FSUS M/IISO
PRTIM
TM PM OXFR
r rw rw
8 7 6
GONA GINAK NPTXF
Res.
KEFFM EFFM
rw rw
RM0390 Rev 4
21 20 19 18
IISOIX OEPIN
IEPINT
FRM T
M
rw rw rw rw
5 4 3 2
RXFLV OTGIN
SOFM
EM LM T
rw rw rw rw
21 20 19 18
IISOIX OEPIN
IEPINT
FRM T
M
rw rw rw rw
5 4 3 2
RXFLV OTGIN
SOFM
EM LM T
rw rw rw rw
17 16
Res. Res.
1 0
MMISM Res.
rw
17 16
Res. Res.
1 0
MMISM Res.
rw
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