Otg_Fs/Otg_Hs Registers; Otg Control And Status Register (Otg_Gotgctl); Table 227. Power And Clock Gating Control And Status Registers - ST STM32F446 Series Reference Manual

RM0390
...
Device IN endpoint x
Device OUT endpoint x
1. Where x is 5[FS] / 8[HS]in device mode and 11[FS] / 15[HS]in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
Acronym
OTG_PCGCCTL
31.15

OTG_FS/OTG_HS registers

These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
31.15.1

OTG control and status register (OTG_GOTGCTL)

Address offset: 0x000
Reset value: 0x0001 0000
The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG
function of the core.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. EHEN
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Table 226. Data FIFO (DFIFO) access register map (continued)
FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 227. Power and clock gating control and status registers

Offset address
0xE00–0xE04
28 27 26 25
Res. Res. Res.
12 11 10 9
DHNP HSHNP HNP
EN EN RQ
rw rw rw rw
(1)
: DFIFO write access
(1)
: DFIFO read access
Section 31.15.60: OTG power and clock gating control
register (OTG_PCGCCTL)
24 23 22
Res. Res. Res.
MOD
8 7 6
HNG BVALO BVALO AVALO
SCS VAL EN
r rw rw
RM0390 Rev 4
Offset address
...
0xX000–0xXFFC
Register name
21 20 19 18
CUR OTG
BSVLD ASVLD
VER
r rw r r
5 4 3 2
AVALO VBVAL VBVAL
VAL EN OVAL OEN
rw rw rw rw
Access
...
w
r
17 16
CID
DBCT
STS
r r
1 0
SRQ
SRQ
SCS
rw r
1111/1328
1264