Otg Receive Status Debug Read/Otg Status Read And Pop Registers (Otg_Grxstsr/Otg_Grxstsp) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Bit 3 SOFM: Start of frame mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both device and host modes.
Bit 2 OTGINT: OTG interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both device and host modes.
Bit 1 MMISM: Mode mismatch interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both device and host modes.
Bit 0 Reserved, must be kept at reset value.
31.15.8 OTG receive status debug read/OTG status read and
pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
Address offset for read: 0x01C
Address offset for pop: 0x020
Reset value: 0x0000 0000
A read to the receive status debug read register returns the contents of the top of the
receive FIFO. A read to the receive status read and pop register additionally pops the top
data entry out of the Rx FIFO.
The receive status contents must be interpreted differently in host and device modes. The
core ignores the receive status pop/read when the receive FIFO is empty and returns a
value of 0x0000 0000. The application must only pop the receive status FIFO when the
receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is
asserted.
Host mode:
31 30 29
Res. Res. Res. Res.
15 14 13
DPID
r r r
1132/1328
28 27 26 25
Res. Res. Res.
12 11 10 9
BCNT
r r r r
24 23 22
Res. Res. Res.
8 7 6
r r r
RM0390 Rev 4
21 20 19 18
Res. PKTSTS[3:0]
r r r
5 4 3 2
r r r r
RM0390
17 16
DPID
r r
1 0
CHNUM
r r