Table 224. Host-Mode Control And Status Registers (Csrs) - ST STM32F446 Series Reference Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
Table 223. Core global control and status registers (CSRs) (continued)
Acronym
OTG_GRXSTSR
OTG_GRXSTSP
OTG_GRXFSIZ
OTG_HNPTXFSIZ/
(1)
OTG_DIEPTXF0
OTG_HNPTXSTS
OTG_GCCFG
OTG_CID
OTG_GLPMCFG
OTG_HPTXFSIZ
OTG_DIEPTXFx
OTG_DIEPTXFx
1. The general rule is to use OTG_HNPTXFSIZ for host mode and OTG_DIEPTXF0 for device mode.
Host-mode CSR map
These registers must be programmed every time the core changes to host mode.

Table 224. Host-mode control and status registers (CSRs)

Acronym
OTG_HCFG
OTG_HFIR
OTG_HFNUM
OTG_HPTXSTS
OTG_HAINT
OTG_HAINTMSK
1106/1328
Address
offset
0x01C
Section 31.15.8: OTG receive status debug read/OTG status read and pop
registers (OTG_GRXSTSR/OTG_GRXSTSP)
0x020
0x024 Section 31.15.9: OTG receive FIFO size register (OTG_GRXFSIZ)
Section 31.15.10: OTG host non-periodic transmit FIFO size register
0x028
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
Section 31.15.11: OTG non-periodic transmit FIFO/queue status register
0x02C
(OTG_HNPTXSTS)
0x038 Section 31.15.12: OTG general core configuration register (OTG_GCCFG)
0x03C Section 31.15.13: OTG core ID register (OTG_CID)
0x54 Section 31.15.14: OTG core LPM configuration register (OTG_GLPMCFG)
Section 31.15.15: OTG host periodic transmit FIFO size register
0x100
(OTG_HPTXFSIZ)
0x104
Section 31.15.16: OTG device IN endpoint transmit FIFO size register
0x108
(OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO number)
...
USB_OTG FS
0x114
0x104
Section 31.15.16: OTG device IN endpoint transmit FIFO size register
0x108
(OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the FIFO number)
...
USB_OTG HS
0x120
Offset
address
0x400 Section 31.15.18: OTG host configuration register (OTG_HCFG)
0x404 Section 31.15.19: OTG host frame interval register (OTG_HFIR)
Section 31.15.20: OTG host frame number/frame time remaining register
0x408
(OTG_HFNUM)
Section 31.15.21: OTG_Host periodic transmit FIFO/queue status register
0x410
(OTG_HPTXSTS)
0x414 Section 31.15.22: OTG host all channels interrupt register (OTG_HAINT)
Section 31.15.23: OTG host all channels interrupt mask register
0x418
(OTG_HAINTMSK)
Register name
Register name
RM0390 Rev 4
RM0390
for
for