Time Triggered Communication Mode; Reception Handling; Figure 390. Transmit Mailbox States - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus
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Controller area network (bxCAN)
30.7.2

Time triggered communication mode

In this mode, the internal counter of the CAN hardware is activated and used to generate the
Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx
and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to
Section 30.7.7: Bit
Of Frame bit in both reception and transmission.
30.7.3

Reception handling

For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see
1040/1328

Figure 390. Transmit mailbox states

timing). The internal counter is captured on the sample point of the Start
Section 30.7.4: Identifier
RM0390 Rev 4
RM0390
filtering.

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