Dma Usage; Dma Register At Mb88121; Dma At Mb91460 - Fujitsu MB88121 Application Note

32-bit microcontroller

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3.3 DMA usage

To fasten payload data access, the MB88121 supports DMA request for Input and Output

buffer transfer.

The lower 16-bit (Bit 15..0) of the CUS2 Register (Adr. 0x08 => 0x50.0008) are used to

control the DMA request feature of MB88121.

The DMAINV bit selects the Active Level (High or Low), the DMAOE bit select if DAM

request is output to a pin. The DMARE bit enables the interrupt request.

See also the Users Guide of MB88121 series.

The MB91460 series DMA supports different transfer modes. In this example we are using

2-cycle transfer type: data is read from an address and then written to another address. The

Fly-by transfer type is suitable for DMA function between external I/O and external memory.

Therefore register IOWR is not used.

For further details see Hardware Manual of MB91460 series and Application note mcu-an-

300059-e-mb91460_dma.

Using the DMA following needs to be encountered:

The MB88121 is connected to the external transfer request pin "DREQ0" in our example. So

this DMA bus interface transfer needs to be setup.

Following settings have to be selected:

Source address

Destination address

Increment / decrement source / destination address

Data length

Number of data transmissions (data count)

DMA channel assignment

Transfer type

MCU-AN-300016-E-V10

Interfacing MB91460 TO MB88121

Chapter 3 Software

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Mb91460