Exposed Pad* (E-Pad*) Design And Smt Assembly Guide; Overview; Pcb Design Requirements - Intel Quark SoC X1000 Design Manual

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Exposed Pad* (e-Pad*) Design and SMT Assembly Guide—Intel
Appendix B Exposed Pad* (e-Pad*) Design and SMT
Assembly Guide
B.1

Overview

This section provides general information about ePAD and SMT assemblies. Chip
packages have exposed die pads on the bottom of each package to provide electrical
interconnections with the printed circuit board. These ePADs also provide excellent
thermal performance through efficient heat paths to the PCB.
Packages with ePADs are very popular due to their low cost. Note that this section only
provides basic information and references in regards to the ePAD. It is recommended
that each customer consult their Fab and assembly house to obtain more details on
how to implement the ePAD package design. Each fab and assembly house might need
to tune the land pattern/stencil and create a solution that best suits their methodology
and process.
B.2

PCB Design Requirements

In order to maximize both heat removal and electrical performance, a land pattern
must be incorporated on the PCB within the footprint of the package corresponding to
the exposed metal pad or exposed heat slug of the package as shown in the following
figures. Refer to the specific product datasheet for actual dimensions.
Note:
Due to the package size, a via-in-pad configuration must be used Figure 101 and Figure
102 are general guidelines see Figure 103 for -specific via-in-pad thermal pattern
recommendations.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Intel
Quark™ SoC X1000
PDG
181

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