Isa (82380Ab); Ich Gpio Connected To 82380Ab; Sub Class Code; Ioapic Design Recommendation - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
Recommended USB trace characteristics
•
Impedance 'Z
•
Line Delay = 160.2 ps
•
Capacitance = 3.5 pF
•
Inductance = 7.3 nH
•
Res @ 20° C = 53.9 mOhm
2.16

ISA (82380AB)

2.16.1

ICH GPIO connected to 82380AB

At reset, the ICH LPC Bridge defaults to subtractive decode. Since the LPC bridge logically sits on
PCI there will be two subtractive decode bridges in systems with the 82380AB (which is also a
subtractive decode device). A GPO that defaults high (i.e., ICH GPO 21) must be connected to the
NOGO signal on the 82380AB. Asserting NOGO prevents the 82380AB from subtractively
decoding cycles on the PCI bus. The BIOS must configure the 82380AB, program the ICH to
positively decode LPC cycles, and release the NOGO signal to the 82380AB.
2.16.2

Sub Class Code

Both the LPC Bridge and the 82380AB have the same Sub Class code indicating an ISA bridge.
This can not be handled by the OS's PCI PnP code. The ICH provides the ability to hide IDSEL to
the 82380AB. ICH A22 must be connected to the 82380AB IDSEL signal. After the BIOS
configures the 82380AB, it will set a bit in the ICH that hides the 82380AB from the OS by not
asserting the IDSEL (A22) to the 82380AB during OS enumeration.
2.17

IOAPIC Design Recommendation

UP systems not using the IOAPIC should follow these recommendations:
•
On the ICH
— Connect PICCLK directly to ground
— Connect PICD0, PICD1 to ground through a 10 KΩ resistor
•
On the CPU
— PICCLK must be connected from the clock generator to the PICCLK pin on the processor
— Connect PICD0 to 2.5V through 10 KΩ resistors
— Connect PICD1 to 2.5V through 10 KΩ resistors
2-66
' = 45.4 Ω
0
®
Intel 820 Chipset Design Guide