Intel ® 855Gme Chipset Gmch (82855Gme) Checklist; System Memory; Gmch System Memory Interface Checklist - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Schematic Checklist Summary
®
12.3 Intel
Checklist
12.3.1

System Memory

12.3.1.1

GMCH System Memory Interface Checklist

Table 121
voltage level for SMVREF.
Table 121. GMCH System Memory Interface Checklist (Sheet 1 of 2)
Pin Name
SRCVENIN#
SRCVENOUT#
SBA[1:0]
SCAS#
SRAS#
SWE#
SCKE[1:0]
SCKE[3:2]
SCS#[1:0]
SCS#[3:2]
SDQ[63:0]
SDM[7:0]
SDQS[7:0]
SDQ[71:64]
SDM8
272
®
6300ESB ICH Embedded Platform Design Guide
855GME Chipset GMCH (82855GME)
presents the GMCH system memory interface checklist.
System
Pull-up/Pull-down
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
56 Ω pull-up to
V_1P25_MEMVTT
Figure 150
Series
Resistor
This signal shall be routed to a via next to
ball and left as a NC.
This signal shall be routed to via next to
ball and left as a NC.
Connect to DIMM 0 and DIMM 1.
Connect to DIMM 0 and DIMM 1.
Connect to DIMM 0 and DIMM 1.
Connect to DIMM 0 and DIMM 1.
Connect to DIMM 0
Connect to DIMM 1
Connect to DIMM 0
Connect to DIMM 1
10 Ω
Connect to DIMM 0 and DIMM 1.
10 Ω
Connect to DIMM 0 and DIMM 1.
10 Ω
Connect to DIMM 0 and DIMM 1.
When ECC support is not implemented,
SDQ[71:64], SDM8, and SDQS8 shall be
10 Ω
left as NC. For ECC support, these signals
connect to DIMMs.
When ECC support is not implemented,
SDQ[71:64], SDM8, and SDQS8 shall be
10 Ω
left as NC. For ECC support, these signals
connect to DIMMs.
depicts the reference
√
Notes