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2
Interfaces
This chapter describes the interfaces supported by the processor.
2.1
System Memory Interface
2.1.1
System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two,
independent, 64-bit wide channels each accessing one SO-DIMM. It supports a
maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up to
two device ranks per-channel.
DDR3 Data Transfer Rates:
— 800 MT/s (PC3-6400) and 1066 MT/s (PC3-8500)
•
DDR3 SO-DIMM Modules:
— Raw Card A – double-sided x16 unbuffered non-ECC
— Raw Card B – single-sided x8 unbuffered non-ECC
— Raw Card C – single-sided x16 unbuffered non-ECC
— Raw Card D – double-sided x8 (stacked) unbuffered non-ECC
— Raw Card F – double-sided x8 (planar) unbuffered non-ECC
•
DDR3 DRAM Device Technology:
— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16
and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If one
side of a memory module is populated, the other side is either identical or
empty.
Table 2-1. Supported SO-DIMM Module Configurations
Raw
DIMM
Card
Capacity
Version
Technology
A
1 GB
A
2 GB
B
1 GB
B
2 GB
C
512 MB
C
1 GB
20
DRAM
DRAM
Device
Organization
1 Gb
64 M x 16
2 Gb
128 M x 16
1 Gb
128 M x 8
2 Gb
256 M x 8
1 Gb
64 M x 16
2 Gb
128 M x 16
1
# of
# of Row/
# of
Physical
DRAM
Device
Address
Devices
Ranks
8
2
13/10
8
2
14/10
8
1
14/10
8
1
15/10
4
1
13/10
4
1
14/10
Interfaces
# of
Col
Banks
Page
Inside
Size
Bits
DRAM
8
8K
8
8K
8
8K
8
8K
8
8K
8
8K
Datasheet
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