Interrupt Mask Registers 0 To 6 (Imr0 To Imr6); Figure 7-11: Interrupt Mask Registers 0 To 2 (Imr0 To Imr2) - NEC V850E/PH2 User Manual

7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6)

The IMR0 to IMR6 registers set the interrupt mask state for the maskable interrupts. The IMK0 to
IMK104 bits are equivalent to the MKn bit in the corresponding PICn register.
The IMRm register (m = 0 to 6) can be read or written in 16-bit units.
If the higher 8 bits of the IMRm register are used as the IMRmH register and the lower 8 bits as the
IMRmL register, these registers can be read or written in 8-bit or 1-bit units.
Reset input sets these registers to FFFFH.
Bits 15 to 9 of the IMR6 register (bits 7 to 1 of the IMR6H register) are fixed to 1. If these bits are not 1,
the operation cannot be guaranteed.
Caution: The device file defines the MKn bit as a reserved word. If a bit is manipulated using
the name of MKn, the contents of the PICn register, instead of the IMRm register, are
rewritten (as a result, the contents of the IMRm register are also rewritten).

Figure 7-11: Interrupt Mask Registers 0 to 2 (IMR0 to IMR2)

After reset: FFFFH
15
IMR0 MK15
7
MK7
After reset: FFFFH
15
IMR1 MK31
7
MK23
After reset: FFFFH
15
IMR2 MK47
7
MK39
IMKn
0
1
Remark: n = 0 to 105 (see Table 7-1)
240
Chapter 7 Interrupt/Exception Processing Function
R/W
14 13
MK14 MK13
6 5
MK6 MK5
R/W
14 13
MK30 MK29
6 5
MK22 MK21
R/W
14 13
MK46 MK45
6 5
MK38 MK37
Enable interrupt servicing
Disable interrupt servicing (pending)
User's Manual U16580EE3V1UD00
Address: IMR0 FFFFF100H
IMR0L FFFFF100H, IMR0H FFFFF101H
12 11
MK12 MK11
4 3
MK4 MK3
Address: IMR1 FFFFF102H
IMR1L FFFFF102H, IMR1H FFFFF103H
12 11
MK28 MK27
4 3
MK20 MK19
Address: IMR2 FFFFF104H
IMR2L FFFFF104H, IMR2H FFFFF105H
12 11
MK44 MK43
4 3
MK36 MK35
Interrupt Mask Flag
10 9
MK10 MK9 MK8
2 1
MK2 MK1 MK0
10 9
MK26 MK25 MK24
2 1
MK18 MK17 MK16
10 9
MK42 MK41 MK40
2 1
MK34 MK33 MK32
8
0
8
0
8
0