NEC V850E/PH2 User Manual page 440

Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (2/3)
(c) TRnCCR1 to TRnCCR3 = TRnCCR0
When the values of TRnCCR1 to TRnCCR3 are changed from "TRnCCR0 − TRnDTC1 <
TRnCCR1 to TRnCCR3 ≤ TRnCCR0" to "TRnCCR0 − TRnDTC1 × 2 < TRnCCR1 to TRnCCR3 <
TRnCCR0 − TRnDTC1", the negative phase will be 100% output for one cycle, as shown in figure
below.
To prevent this phenomenon, change "TRnCCR0 − TRnDTC1 < TRnCCR1 to TRnCCR3 ≤
TRnCCR0" to "TRnDTC0 < TRnCCR1 to TRnCCR3 < TRnDT1 × 2" through "TRnCCR0 −
TRnDTC1", or directly change "TRnCCR0 − TRnDTC1 < TRnCCR1 to TRnCCR3 < TRnCCR0" to
"TRnCCR1 to TRnCCR3 ≤ TRnCCR0 − TRnDTC1 × 2".
TRnCCR1 to TRnCCR3
TRnCCR0
16-bit sub-counter
0000H
TRnDTT1 to TRnDTT3
TORn1, TORn3,
TORn5
TORn2, TORn4,
TORn6
(d) TRnCCR1 to TRnCCR3 = TRnCCR0
TRnCCR1 to TRnCCR3
TRnCCR0
16-bit counter
0000H
TRnDTT1 to TRnDTT3
TORn1, TORn3,
TORn5
TORn2, TORn4,
TORn6
440
Chapter 10 16-bit Inverter Timer/Counter R
→
TRnCCR0
TRnCCR0
16-bit sub-counter
"L"
SB3
→
TRnCCR0
16-bit sub-counter
SB3
User's Manual U16580EE3V1UD00
−
TRnDTC1 x 2 < TRnCCR1 to TRnCCR3
−
TRnDTC1
RT2
SB1
RB1
TRnDTC0 + TRnDTC1 < TRnCCR1 to TRnCCR3 <
−
TRnDTC1 x 2
ST2 RT2 ST2
RB3 SB2 RB2
RT2
SB1
RB1
RT2 ST2
SB2 RB2
<