NEC V850E/PH2 User Manual page 47

(6) Clock generator (CG)
The CG provides a frequency that is 4 times the input clock (f
internal system clock (f
and X2 or input an external clock from the X1 pin.
(7) Real-time pulse unit (RPU)
The RPU incorporates a 2-channel 16-bit timer (TMR) for 3/6-phase sine wave PWM inverter
control, an 1-channel 16-bit up/down counter (TMENC10), μPD70F3187 only and a 2-channel
16-bit up/down counter (TMT) that can be used for 2-phase encoder input or as a general-purpose
timer, a 9-channel 16-bit general-purpose timer unit (TMP).
The RPU can measure pulse interval or frequency and can output programmable pulses.
(8) Serial interface (SIO)
The serial interfaces consist of 2 channels asynchronous serial interface C (UARTC), up to 2
channels clocked serial interface B (CSIB), up to 2 channels clocked serial interface 3 (CSI3), and
up to 2 channels FCAN interface (AFCAN).
The UARTC performs data transfer using pins TXDCn and RXDCn (n = 0, 1).
The CSIB performs data transfer using pins SOBn, SIBn, SCKBn, SSIn, and SSOn
The CSI3 performs data transfer using pins SO3n, SI3n, SCK3n, SCS3n0 to SCS3
The AFCAN performs data transfer using pins FCTXDn and FCRXDn
(9) Baud rate generator (BRG)
The baud rate generator comprises 3 channels of 8-bit counters and comparators that can be
used for clock supply of serial interfaces (CSIB), auxiliary frequency output (AFO) or interval timer.
(10) A/D converter (ADC)
The two units of high-speed, high-resolution 10-bit A/D converter include 10 analog input pins for
each unit. Conversion is performed using the successive approximation method.
(11) Random number generator (RNG)
For encryption purpose a random number generator is provided.
(12) Debug control unit (DCU)
On-chip debugging can be performed via a debug control unit (n-wire interface).
Notes: 1. n = 0, 1 for μPD70F3187
n = 0 for μPD70F3447
2. Not available on µPD70F3447
Chapter 1 Introduction
). As the input clock, connect an external crystal or resonator to pins X1
CPU
User's Manual U16580EE3V1UD00
) (using the on-chip PLL) as the
X
Note1
Note1
Note1
.
.
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