Table 10-2: Tmrn Count Clock And Count Delay - NEC V850E/PH2 User Manual

Figure 10-12: TMRn Control Register 0 (TRnCTL0) (2/2)
TRnCKS2 TRnCKS1 TRnCKS0
0
0
0
0
1
1
1
1
Caution: Set bits TRnCKS2 to TRnCKS0 when TRnCE = 0.
Remark: f
Remark: n = 0, 1
Count TTnCKS2
Clocks
f /2 0
XX
f /4 0
XX
f /8 0
XX
f /16 0
XX
f /32 1
XX
f /64 1
XX
f /256 1
XX
f /1024 1
XX
Remarks: 1. : System clock
f
XX
2. f : Base clock of timer Rn (f
TMRn
3. n = 0, 1
Chapter 10 16-bit Inverter Timer/Counter R
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
When bit TRnCE is set from 0 to 1, bits TRnCKS2 to TRnCKS0 can be
simultaneously set.
: System clock
XX

Table 10-2: TMRn Count Clock and Count Delay

TTnCKS1 TTnCKS0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
TMRn
User's Manual U16580EE3V1UD00
Internal Count Clock Selection of Timer Rn
f /2
XX
f /4
XX
f /8
XX
f /16
XX
f /32
XX
f /64
XX
f /256
XX
f /1024
XX
Count Delay
Minimum
3 base clocks
4 base clocks
= f /2)
XX
Maximum
4 base clocks
5 base clocks
+
1 count clock
325