Single Mode (Slave Mode, Transmission/Reception Mode); Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode) - NEC V850E/PH2 User Manual

17.6.6 Single mode (slave mode, transmission/reception mode)

Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode)

Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B)
Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
CTXEn bit,
CRXEn bit
SFDB3n
register write
SFEMPn flag
CSIBUF3n [0]
CSIBUF3n [1]
CSIBUF3n [2]
SCK3n pin
SO3n pin
SI3n pin
SCS3n0 to
H (inactive level)
SCS3n3 pins
CSOTn flag
INTC3n signal
SIRB3n
register
SIRB3n
register read
SFP3 to
0H
SFP0 bits
<1> <5>
<2>
<3> Note 1
<4>
Notes: 1. During this period a transmission/reception from the master will be ignored until at least one
transmit data is loaded to the CSIBUFn register by writing the SFDB3n register (SFEMPn
flag of SFA3n register = 0).
2. While the SIRB3n register is full a new transmission/reception from the master will be
ignored until the SIRB3n register is read.
μPD70F3187:
Remark:
μPD70F3447:
724
Chapter 17 Clocked Serial Interface 3 (CSI3)
MSB First (DIR bit = 0), CKP bit = 0, DAP bit = 1
INTC3n Interrupt Not Delayed (CSIT bit = 0),
Transfer Wait: Disabled (CSWE bit = 0),
55H
AAH
0 1 0 1 0 1 0 1 1
1 1 0 0 1 1 0 0
1H 2H 1H
<6> <6>
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00
0 1 0 1 0 1 0
1 0 0 1 0 1 1 0
CCH
<7>
Note 2
33H
0 0 1 1 0 0
1 0 0 1 1
96H
0H 1H
<6> <7>
Note 1
1 1
0 0 1
99H
0H
<7>
<8>