Restore; Figure 7-7: Reti Instruction Processing - NEC V850E/PH2 User Manual

7.3.2 Restore

Recovery from maskable interrupt processing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to
the address of the restored PC.
(1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the
PSW is 0 and the NP bit of the PSW is 0.
(2) Transfers control to the address of the restored PC and PSW.
Figure 7-7 illustrates the processing of the RETI instruction.
1
PC
PSW
Note: For the ISPR register, see 7.3.6 "In-service priority register (ISPR)" on page 242.
Caution: When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction
during maskable interrupt processing, in order to restore the PC and PSW correctly
during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and
PSW.NP back to 0 using the LDSR instruction immediately before the RETI
instruction.
Remark: The solid lines show the CPU processing flow.
Chapter 7 Interrupt/Exception Processing Function

Figure 7-7: RETI Instruction Processing

RETI instruction
PSW.EP
0
PSW.NP
0
EIPC
EIPSW
Restores original processing
User's Manual U16580EE3V1UD00
1
PC
PSW
FEPC
FEPSW
231