Pulse Width Measurement Mode; Figure 11-33: Basic Operation Timing In Pulse Width Measurement Mode - NEC V850E/PH2 User Manual

11.6.7 Pulse width measurement mode

In the pulse width measurement mode, counting is performed in the free-running mode. The counter
value is saved to the TTnCCR0 register, and the counter is cleared to 0000H. As a result, the external
input pulse width can be measured. However, when measuring a long pulse width that exceeds counter
overflow, perform judgment with the overflow flag. Measurement of pulses during which overflow occurs
twice or more is not possible, so adjust the counter's operating frequency. Even in the case of TITn1 pin
edge detection, pulse width measurement can be similarly performed by using the TTnCCR1 register.
Cautions: 1. In the pulse width measurement mode the external event clock input (TEVTTn) is
prohibited (TTnCTL1.TTnEEE = 0).
2. When an internal count clock ≤ f
width measurement mode, and a valid signal edge is input before the first count
up, the a value of FFFFH will be captured in the corresponding TTnCCR0 or
TTnCCR1 register.

Figure 11-33: Basic Operation Timing in Pulse Width Measurement Mode

FFFFH
Counter
TTnCE
TITn0
TTnCCR0 0000H
INTTTnCC0
TTnOVF
INTTTnOV
Remarks: 1. D , D
00 01
2. TITn0: Setting to rising edge/falling edge (both edges) detection (TTnIOC1 register
bits TTnIS1, TTnIS0 = 1B)
3. n = 0, 1
Chapter 11 16-bit Timer/Event Counter T
(a) (TTnOE0, 1 = 0, TTnOL0, 1 = 0)
D
01
D
00
D
00
, D , D : Values captured to TTnCCR0 register (0000H to FFFFH)
02 03
User's Manual U16580EE3V1UD00
/16 (TTnCTL0.TTnCKS2-0) is selected in pulse
XX
D
02
D
01
FFFFH
D
03
D D
02
Cleared through 0
write from CPU
03
511