Table of Contents
Advertisement
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.5 Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3)
These registers set the interrupt mask status for maskable interrupts. The xxMKn bit of the IMR0, IMR1, and IMR3
registers and the xxMKn bit of the xxlCn register are respectively linked.
The IMRm register can be read or written in 16-bit units (m = 0, 1, 3).
When the higher 8 bits of the IMRk register are treated as the IMRkH register and the lower 8 bits of the IMRk
register as the IMRkL register, they can be read or written in 8-bit or 1-bit units (k = 0, 1).
Caution In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if
bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register,
is rewritten (as a result, the IMRm register is also rewritten).
After reset: FFFFH
Note
IMR0 (IMR0H
)
(IMR0L)
After reset: FFFFH
Note
IMR1 (IMR1H
)
(IMR1L)
After reset: FFFFH
IMR3
(IMR3L)
Note When reading from or writing to bits 8 to 15 of the IMR0 and IMR1 registers in 8-bit or 1-
bit units, specify these bits as bits 0 to 7 of the IMR0H and IMR1H registers.
Caution Set bits 9 and 8 of the IMR0 register, bits 15 and 8 of the IMR1 register, and bits
Remark
R/W
Address: IMR0 FFFFF100H,
15
14
13
CSI0MK1
CSI0MK0
TM5MK1
7
6
5
PMK6
PMK5
PMK4
R/W
Address: IMR1 FFFFF102H,
15
14
13
1
BRGMK
WTMK
7
6
5
TMHMK1
TMHMK0
STMK1
R/W
Address: IMR3, IMR3L FFFFF106H
15
14
13
1
1
1
7
6
5
1
1
1
xxMKn
0
Enables interrupt servicing
1
Disables interrupt servicing
15 to 5 of the IMR3 register to 1. The operation is not guaranteed if their value
is changed.
xx: Identifying name of each peripheral unit (refer to Table 17-2 Interrupt Control
Registers (xxICn))
n: Peripheral unit number (refer to Table 17-2 Interrupt Control Registers (xxICn))
User's Manual U16896EJ2V0UD
IMR0L FFFFF100H, IMR0H FFFFF101H
12
11
10
TM5MK0
TM0MK11
TM0MK10
4
3
2
PMK3
PMK2
PMK1
IMR1L FFFFF102H, IMR1H FFFFF103H
12
11
10
WTIMK
KRMK
ADMK
4
3
2
SRMK1
SREMK1
STMK0
12
11
10
1
1
1
4
3
2
TP0CCMK1
TP0CCMK0
TP0OVMK
Interrupt mask flag setting
9
8
1
1
1
0
PMK0
WDT1MK
9
8
IICMK0
1
1
0
SRMK0
SREMK0
9
8
1
1
1
0
PMK7
LVIMK
549
Advertisement
Table of Contents
