Figure 6-13: Dma Channel 2 And 3 Trigger Signal Timing - NEC V850E/PH2 User Manual

Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing

Setup MARx, DTCRx,
SARx register
INTTRnOD
or
INTTRnCD
DMA transfer
MARx
SARx
DTCRx
INTDMAx
Remarks: 1. The DMA request by INTTRnOD or INTTRnCD is disregarded after INTDMAx is gener-
ated, and the DMA transfer is not restarted automatically. Write "1" in the corresponding
DEx bit of the DMAMC register again to enable the next transfer of DMA channel x. The
DEx bit is not cleared by hardware.
2. n = 0, 1
x = n+2
Chapter 6 DMA Functions (DMA Controller)
1000H 1002H 1004H
04H 05H 06H
02H
(number of the TMR channel)
(number of the DMA channel)
User's Manual U16580EE3V1UD00
1006H 1008H 100AH
07H 04H 05 H
01H
100EH 1010H
07H 04H
0H
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