NEC V850E/PH2 User Manual page 478

TTnEOF
0
1
If the counter value is counted up from FFFFH, overflow occurs, the OVF flag is set (1),
and the counter is cleared to 0000H. At the same time that the TTnEOF flag is set (1), an
overflow interrupt (INTTTnOV) occurs. However, the TTnOVF flag is not set (to 1).
The TTnEOF flag is cleared (0) under the following conditions.
• When 0 is written by CPU instruction
• When TTnCE = 0 is set while TTnECC = 0
Cautions: 1. The TTnEOF flag is not cleared even if it is read.
Remark: When bit TTnECC of the TTnCTL2 register is 1, the flag status is held even if
TTnESF
0
1
The TTnESF flag is cleared (to 0) under the following conditions.
• When TTnCE = 0 is set while TTnECC = 0
Remark: When bit TTnECC of the TTnCTL2 register is 1, the flag status is held even if
Remark: n = 0, 1
478
Chapter 11 16-bit Timer/Event Counter T
Figure 11-14: TMTn Option Register 1 (TTnOPT1) (2/2)
No overflow indicated
Indicates counter overflow in the encoder compare mode
2. The TTnEOF flag can be read and written, but even if 1 is written to
the TTnEOF flag from the CPU, this is invalid.
the value of bit TTnCE is changed from 1 to 0.
Indicates the up count operation of the counter in the encoder compare mode.
Indicates the down count operation of the counter in the encoder compare
mode.
the value of bit TTnCE is changed from 1 to 0.
User's Manual U16580EE3V1UD00
Indication of Encoder Overflow
Indication of Encoder Count Direction