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8.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
These registers set the interrupt mask state for the maskable interrupts.
The xxMK bit of the IMR0 to IMR3 registers is equivalent to the xxMK bit of the xxIC register.
IMRm registers can be read/written in 16-bit units (m = 0 to 3).
When the IMRm register is divided into two registers: higher 8 bits (IMRmH register) and lower 8 bits
(IMRmL register), these registers can be read/written in 8-bit or 1-bit units (m = 0 to 3).
The address of the lower 8-bit register IMRmL is equal to that of the 16-bit IMRm register, and the
higher 8-bit register IMRmH can be accessed on the following address (address (IMRm) + 1).
Figure 8-11: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
15
14
IMR0
GCC03MK GCC02MK GCC01MK GCC00MK TMG01MK TMG00MK
7
6
P3MK
P2MK
15
14
IMR1
FC1RXMK MACMK
7
6
GCC13MK GCC12MK GCC11MK GCC10MK TMG11MK TMG10MK GCC05MK GCC04MK
15
14
IMR2
SR0MK
SER0MK
7
6
FC3ERMK FC3TXMK FC3RXMK FC2ERMK FC2TXMK FC2RXMK FC1ERMK FC1TXMK
15
14
IMR3
1
P21MK
7
6
DMA3MK DMA2MK DMA1MK DMA0MK
Bit Position
Bit Name
15 to 0
xxMK
Remark:
xx: Identification name of each peripheral unit (WT, TMD, P, TMG, GCC, AD, MAC, FC, CSI,
UART, DMA)
Chapter 8 Interrupt/Exception Processing Function
13
12
5
4
P1MK
P0MK
13
12
ADMK
CCC01MK CCC00MK TMC0MK GCC15MK GCC14MK
5
4
13
12
CSI2MK
CSI1MK
5
4
13
12
P20MK
P15MK
5
4
Interrupt mask flag.
0: Interrupt servicing enabled
1: Interrupt servicing disabled (pending)
Preliminary User's Manual U15839EE1V0UM00
11
10
9
P5MK
3
2
1
WTIMK
TMD1MK TMD0MK
11
10
9
3
2
1
11
10
9
CSI0MK FC4ERMK FC4TXMK FC4RXMK
3
2
1
11
10
9
P10MK
P05MK
P00MK
3
2
1
ST1MK
SR1MK
SER1MK
Function
8
Address
P4MK
FFFFF100H
0
WTMK
8
Address
FFFFF102H
0
8
Address
FFFFF104H
0
8
Address
DOVFMK
FFFFF106H
0
ST0MK
Initial value
FFFFH
Initial value
FFFFH
Initial value
FFFFH
Initial value
FFFFH
219
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