Table 18-3: Settable Bit Rate Combinations - NEC V850E/PH2 User Manual

<~Reference>Table 18-3 shows the combinations of bit rates that satisfy the above conditions.
SYNC
DBT length
SEGMENT
25 1
24 1
24 1
23 1
23 1
23 1
22 1
22 1
22 1
22 1
21 1
21 1
21 1
21 1
21 1
20 1
20 1
20 1
20 1
20 1
20 1
19 1
19 1
19 1
19 1
19 1
19 1
19 1
18 1
18 1
18 1
18 1
18 1
18 1
18 1
18 1
17 1
17 1
Chapter 18 AFCAN Controller

Table 18-3: Settable bit rate combinations (1/3)

Valid bit rate setting
PROP PHASE
SEGMENT SEGMENT1
8
7
9
6
8
10
5
7
9
11
4
6
8
10
12
3
5
7
9
11
13
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
2
4
User's Manual U16580EE3V1UD00
PHASE
SEGMENT2
8 8
8 8
7 7
8 8
7 7
6 6
8 8
7 7
6 6
5 5
8 8
7 7
6 6
5 5
4 4
8 8
7 7
6 6
5 5
4 4
3 3
8 8
7 7
6 6
5 5
4 4
3 3
2 2
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
7 7
6 6
CnBTR register setting
value
TSEG1 TSEG2
[3:0] [2:0]
1111 111
1110 111
1111 110
1101 111
1110 110
1111 101
1100 111
1101 110
1110 101
1111 100
1011 111
1100 110
1101 101
1110 100
1111 011
1010 111
1011 110
1100 101
1101 100
1110 011
1111 010
1001 111
1010 110
1011 101
1100 100
1101 011
1110 010
1111 001
1000 111
1001 110
1010 101
1011 100
1100 011
1101 010
1110 001
1111 000
1000 110
1001 101
Sampling
point
unit (%)
68.0
66.7
70.8
65.2
69.6
73.9
63.6
68.2
72.7
77.3
61.9
66.7
71.4
76.2
81.0
60.0
65.0
70.0
75.0
80.0
85.0
57.9
63.2
68.4
73.7
78.9
84.2
89.5
55.6
61.1
66.7
72.2
77.8
83.3
88.9
94.4
58.8
64.7
833