Figure 6-10: Dma Channel 0 And 1 Trigger Signal Timing - NEC V850E/PH2 User Manual

Figure 6-10: DMA Channel 0 and 1 Trigger Signal Timing

Setup MARx, DTCRx,
DMAMC register
ADDMARQn
DMA transfer
MARx 1000H
DTCRx
0003H
INTADn
Remarks: 1. The DMA request by ADDMARQ is disregarded after INTDMA is generated, and the
DMA transfer is not restarted automatically. Write "1" in the corresponding DEx bit of the
DMAMC register again to enable the next transfer of DMA channel x. The DEx bit is not
cleared by hardware.
2. n = 0, 1
x = n
Chapter 6 DMA Functions (DMA Controller)
1002H 1004H 1006H
0002H 0001H 0000H
(number of the A/D converter channel)
(number of the DMA channel)
User's Manual U16580EE3V1UD00
Re-setup DTCRx, DMAMC
register (write DEx bit = 1)
1008H 100AH
0000H 0003H
100CH 100EH 1010H
0002H 0001H 0000H
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