Figure 11-32: Basic Operation Timing In Free-Running Mode (Compare/Capture Function) - NEC V850E/PH2 User Manual

(3) Compare/capture function (TTnCCS1 = 0, TTnCCS0 = 1)
When TTnCTL0 register bit TTnCE is set to 1, the counter counts from 0000H to FFFFH, an
overflow interrupt (INTTTnOV) is output when the value of the counter changes from FFFFH to
0000H, and the counter is cleared. The count operation is performed in the free-running mode
until TTnCE = 0 is set. The TTnCCR1 register is used as a compare register, and as the interval
function upon a match between the counter and TTnCCR1 register, a compare match interrupt
(INTTTnCC1) is output. Since the TTnCCR0 register is set to the capture function, the TOTn0 pin
cannot be controlled even when TTnIOC0 register bit TTnOE0 is set to 1.
Cautions: 1. In free-running mode the external event clock input (TEVTTn) is prohibited
(TTnCTL1.TTnEEE = 0).
2. When an internal count clock ≤ f
running mode, and TTnCCR0 register is used as capture register, the a value of
FFFFH will be captured if a valid signal edge is input before the first count up.

Figure 11-32: Basic Operation Timing in Free-Running Mode (Compare/Capture Function)

(a) When value of TTnCCR1 is rewritten, TOTn0, TOTn1 are output
FFFFH
Counter
TTnCE
TITn0
TTnCCR0
INTTTnCC0
capture interrupt
TTnCCR1
TTnCCR1
0000H
buffer
INTTTnCC1
Match interrupt
INTTTnOV
overflow interrupt
TOTn0
TOTn1
Remarks: 1. D , D
00 01
D , D
10 11
2. TITn0: Setting to rising edge detection (TTnIOC1 register bits TtnIS1, TtnIS0 = 11)
3. n = 0, 1
Chapter 11 16-bit Timer/Event Counter T
(TTnOE0, 1 = 1, TTnOL0, 1 = 0)
D
00
D
10
0000H
D
10
D
10
Low
: Setting values of TTnCCR1 register (0000H to FFFFH)
, D , D , D , D : Values captured to TTnCCR0 register (0000H to FFFFH)
12 13 14 15
User's Manual U16580EE3V1UD00
/16 (TTnCTL0.TTnCKS2-0) is selected in free-
XX
D
02
D
01
D
11
D D
00 01
D
11
D
11
D
03
D
12
D
11
D D
02 03
D
12
D
12
509