Control Registers; Figure 17-2: Clocked Serial Interface Mode Register 3N (Csim3N) (1/2) - NEC V850E/PH2 User Manual

17.3 Control Registers

(1) Clocked serial interface mode registers 3n (CSIM3n)
The CSIM3n register controls the operation of CSI3n (n = 0, 1).
This registers can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 00H.
Cautions: 1. Writing the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits is enabled only when
CTXEn bit = 0 and CRXEn bit = 0.
2. To use CSI3n, be sure to set the external pins related to the CSI3n function to
control the mode and set the CSIC3n register. Then set the CSICAEn bit to 1
before setting the other bits.

Figure 17-2: Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2)

After reset: 00H
7
CSIM3n CSICAEn
CSICAEn
0
1
Cautions: 1. The CSI3n unit is reset when the CSICAEn bit = 0, and CSI3n is
CTXEn
0
1
Caution:
CRXEn
0
1
Caution:
Note: Not available on
μPD70F3187:
Remark:
μPD70F3447:
680
Chapter 17 Clocked Serial Interface 3 (CSI3)
R/W Address:
6 5
CTXEn CRXEn
Stops clock supply to CSI3n
Supplies clock to CSI3n
stopped. To operate CSI3n, first set the CSICAEn bit to 1.
2. When rewriting the CSICAEn bit from 0 to 1 or from 1 to 0,
simultaneously rewriting the bits other than the CSICAEn bit of the
CSIM3n register is prohibited.
When the CSICAEn bit = 0, rewriting the bits other than the CSICAEn
bit of the CSIM3n register, and the SFDB3n, SFDB3nL, and SFA3n
registers is prohibited.
Disables transmission
Enables transmission
The CTXEn bit is reset when the CSICAEn bit is cleared to 0.
Disables reception
Enables reception
The CRXEn bit is reset when the CSICAEn bit is cleared to 0.
PD70F3447
µ
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00
CSIM30 FFFFFD40H,
CSIM31 FFFFFD60H
4 3
TRMDn DIRn
CSI3n Operation Clock Control
Transmission Operation Enable
Reception Operation Enable
Note
2 1
CSITn CSWEn CSMDn
0