Interrupt Mask Registers 0 To 3 (Imr0 To Imr3) - NEC V850E/MA1 User Manual

32-bit single-chip microcontroller

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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION

7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)

These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3

registers is equivalent to the xxMKn bit of the xxICn register.

The IMRm register (m = 0 to 3) can be read/written in 16-bit units.

If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,

these registers can be read/written in 8-bit or 1-bit units.

Bits 15 to 1 of the IMR3 register (bits 7 to 0 of the IMR3H register and bits 7 to 1 of the IMR3L register) are fixed to

1. If these bits are not 1, the operation cannot be guaranteed.

Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is

manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm

Bit position

(IMR0 to 2),

Remark xx: Identification name of each peripheral unit (OV, P00 to P03, P10 to P13, CM, DMA, CSI, SE, SR,

ST, and AD).

n: Peripheral unit number (None, or 0 to 3)

Interrupt mask flag

0: Interrupt servicing enabled

1: Interrupt servicing disabled (pending)

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