Figure 9-6: Tmpn Control Register 1 (Tpnctl1) (1/2) - NEC V850E/PH2 User Manual

(2) TMPn control register 1 (TPnCTL1)
The TPnCTL1 register is an 8-bit register that controls the operation of timer P.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
TPnCTL1 TPnSYE
(n = 0 to 8)
TPnSYE
0
1
• This bit supports synchronous operation of two or more timer P.
• Two groups of timers exist, which can be synchronized: TMP0 to TMP3 with TMP0 as
master, and TMP4 to TMP7 with TMP4 as master.
Note: Synchronous operation mode is not available for TMP8 (n = 8).
TPnEST
0
1
• The TPnEST bit functions as a software trigger in the one-shot pulse mode and the
external trigger pulse output mode
sure to set TPnEST to 1 after setting TPnCE to 1.
• TTRGPn pin is used as the external trigger input of TMPn.
• The read value of the TPnEST bit is always 0.
Notes: 1. The TRnEST bit is invalid even if it is controlled in any other mode.
Cautions: 1. Always clear the TPnSYE bit for the master timers TMP0 and TMP4.
2. Always clear the TPnSYE bit for TMP8. Do not operate TMP8 in synchronous
mode.
Remark: n = 0 to 8
Chapter 9 16-Bit Timer/Event Counter P

Figure 9-6: TMPn Control Register 1 (TPnCTL1) (1/2)

R/W
6 5
TPnEST TPnEEE
Timer Pn operates in single operation mode
Timer Pn operates in synchronous operation mode
No operation
In one-shot pulse mode: One-shot pulse software trigger
In external trigger pulse output mode: Pulse output software trigger
2. External trigger input pin is not available for TMP8 (n = 8)
User's Manual U16580EE3V1UD00
Address: TP0CTL1 FFFFF601H, TP1CTL1 FFFFF611H,
TP2CTL1 FFFFF621H, TP3CTL1 FFFFF631H,
TP4CTL1 FFFFF641H, TP5CTL1 FFFFF651H,
TP6CTL1 FFFFF661H, TP7CTL1 FFFFF671H,
TP8CTL1 FFFFF681H
4 3
0 0 TPnMD2
Synchronous Mode Selection
Software Trigger Control
Note 1
, if it is set to 1 when TPnCE = 1. Therefore, be
2 1 0
TPnMD1 TPnMD0
Note
Note 2
265