Single Mode (Master Mode, Reception Mode); Figure 17-23: Single Mode (Master Mode, Reception Mode) - NEC V850E/PH2 User Manual

17.6.2 Single mode (master mode, reception mode)

Figure 17-23: Single Mode (Master Mode, Reception Mode)

Transfer Data Length: 8 Bits (CCLn3 to CCLn0 bits = 1000B)
Chip Select Active Level: L-Level (CSLVn3 to CSLVn0 bits = 0000B)
CRXEn bit
SFDB3n
register write
SFEMPn flag
CSIBUF3n [0]
CSIBUF3n [1]
CSIBUF3n [2]
SCK3n pin
SI3n pin
SCS3n0 to
H (inactive)
SCS3n3 pins
CSOTn flag
INTC3n signal
SIRB3n
register
SIRB3n
register read
SFP3 to
0H
SFP0 bits
<1> <5>
<2>
<3>
<4>
Notes: 1. While the SIRB3n register is full a new transfer start of reception from the slave is put on
hold until the SIRB3n register is read.
2. During this period a reception from the slave is put on hold until at least one dummy
transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register
(SFEMPn flag of SFA3n register = 0) in order to start the transfer.
μPD70F3187:
Remark:
μPD70F3447:
716
Chapter 17 Clocked Serial Interface 3 (CSI3)
MSB First (DIR bit = 0), CKP bit = 1, DAP bit = 1
INTC3n Interrupt Not Delayed (CSIT bit = 0),
Transfer Wait: Disabled (CSWE bit = 0),
dummy
dummy
0 1 0 1 0 1 0 1 1
CS0
1H 2H 1H
<6> <6>
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00
0 1 0 1 0 1
0
CS1
55H
0H
<7>
Note 1
dummy
1 1 0 0 1 1
CS2
AAH
1H
<6> <7>
Note 2
0 0
CCH
0H
<7>
<8>