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7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
These registers set the interrupt mask state for the maskable interrupts.
The PMKn bit of the IMR0 to IMR3 registers is equivalent to the PMKn bit of the PICn register.
IMRm registers can be read/written in 16-bit units (m = 0 to 3).
When the IMRm register is divided into two registers: higher 8 bits (IMRmH register) and lower 8 bits
(IMRmL register), these registers can be read/written in 8-bit or 1-bit units (m = 0 to 3).
The address of the lower 8-bit register IMRmL is equal to that of the 16-bit IMRm register, and the
higher 8-bit register IMRmH can be accessed on the following address (address(IMRm) + 1).
Figure 7-12: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
15
14
IMR0
PMK15 PMK14 PMK13 PMK12 PMK11 PMK10
7
6
PMK7
PMK6
15
14
IMR1
PMK31 PMK30 PMK29 PMK28 PMK27 PMK26 PMK25 PMK24
7
6
PMK23 PMK22 PMK21 PMK20 PMK19 PMK18 PMK17 PMK16
15
14
IMR2
PMK47 PMK46 PMK45 PMK44 PMK43 PMK42 PMK41 PMK40
7
6
PMK39 PMK38 PMK37 PMK36 PMK35 PMK34 PMK33 PMK32
15
14
IMR3
1
1
7
6
PMK55 PMK54 PMK53 PMK52 PMK51 PMK50 PMK49 PMK48
Bit Position
Bit Name
15 to 0
PMKn
Remark: n: peripheral unit number (refer to Table 7-2, "Addresses and Bits of Interrupt Control Regis-
ters (Sheet 1 of 2)," on page 203).
Chapter 7 Interrupt/Exception Processing Function
13
12
5
4
PMK5
PMK4
13
12
5
4
13
12
5
4
13
12
1
1
5
4
Interrupt mask flag.
0: Interrupt servicing enabled
1: Interrupt servicing disabled (pending)
Preliminary User's Manual U14913EE1V0UM00
11
10
9
PMK9
3
2
1
PMK3
PMK2
PMK1
11
10
9
3
2
1
11
10
9
3
2
1
11
10
9
PMK59 PMK58 PMK57 PMK56
3
2
1
Function
8
Address
PMK8
FFFFF100H
0
PMK0
8
Address
FFFFF102H
0
8
Address
FFFFF104H
0
8
Address
FFFFF106H
0
Initial
value
FFFFH
Initial
value
FFFFH
Initial
value
FFFFH
Initial
value
FFFFH
205
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