Figure 10-60: Timer Output Example During Operation (High-Accuracy T-Pwm Mode) - NEC V850E/PH2 User Manual

The Figure 10-60 shows the timing chart when TRnCCR0 = 0010H, TRnDTC0 = 0002H,
TRnDTC1 = 0004H, and the TRnCCR1 register is set from 0000H to 0010H (one part only
shown). In this example, TRnOL6 to TRnOL1 = 000000B is set.
As can be seen in this figure, a normal phase (pin TORn1) that is active (high level) is output when
0000H ≤ TRnCCR1 ≤ (TRnCCR0 - TRnDTC0 + 0001H).
Also, the inverted phase (pin TORn0) that is active (high level) is output when
(TRnDTC0 + TRnDTC1) < TRnCCR1 ≤ TRnCCR0.

Figure 10-60: Timer Output Example During Operation (High-Accuracy T-PWM Mode)

Counter
Sub-counter
TRnCE
TRnCUF
TRnSUF
TRnCCR0
TRnDTC0
TRnDTC1
[TRnCCR1 = 0000H]
[TRnCCR1 = 0001H]
[TRnCCR1 = 0002H]
[TRnCCR1 = 0004H]
[TRnCCR1 = 0008H]
[TRnCCR1 = 000AH]
[TRnCCR1 = 000CH]
[TRnCCR1 = 000EH]
[TRnCCR1 = 0010H]
Remarks: 1. TRnCCR0 = 0010H, TRnDTC0 = 0002H, TRnDTC1 = 0004H
2. TD0: Time depends on dead time setting of TRnDTC0 register
TD1: Time depends on dead time setting of TRnDTC1 register
TS0: Time is determined through sub-counter compare, when
sub-counter value < counter value
TS1: Time is determined through sub-counter compare, when
sub-counter value > counter value
3. n = 0, 1
426
Chapter 10 16-bit Inverter Timer/Counter R
00040006 0008
00040002
00000002000400060008
000C 000A
TORn1
"L"
TORn2
TORn1
"L"
TORn2
T
D0
TORn1
TORn2 "L"
T
TORn1 D0
TORn2
TORn1
TORn2
TORn1 "L"
TORn2
"L"
TORn1
TORn2
"L"
TORn1
TORn2
TORn1
TORn2
User's Manual U16580EE3V1UD00
0008000600040002 00040006
000A 000C 000A
0010
000E 000E 000C 000A
0010H (for cycle setting)
002H (for dead time setting)
004H (for dead time setting)
T
D0
T
D1
T
D1
T
S1
0000 0002
T
D1