Noise Elimination; Table 20-23: Noise Elimination - NEC V850E/PH2 User Manual

20.4 Noise Elimination

A timing controller used to secure the noise elimination time is provided for the pins shown in Table
20-23 below. Input signals that change within the noise elimination time are not internally
acknowledged.
Unit
Reset
On-chip debug
Non-maskable interrupt
• Maskable Interrupt
• Forced output stop
function (TMR)
• A/D converter (ADC)
• Maskable Interrupt
• Asynchronous serial
Interface (UART C)
• Maskable Interrupt
• Clocked serial
interface 3 (CSI3)
Timer ENC
Note 1
(TMNEC10)
Notes: 1. Not available on μPD70F3447.
2. No noise elimination on μPD70F3447
Chapter 20 Port Functions

Table 20-23: Noise Elimination (1/2)

Pin
RESET
DRST
P00/NMI
P01/INTP0/ESO0
P02/INTP1/ESO1
P03/INTP2/ADTRG0
P04/INTP3/ADTRG1
P30/RXDC0/INTP4
P32/RXDC1/INTP5
P83/SCS300/INTP6
P84/SCS301/INTP7
P85/SCS302/INTP8
Note 1
P93/SCS310 /INTP9
Note 1
P94/SCS311 /INTP10
Note 1
P95/SCS312 /INTP11
P100/TCLR0/TICC00/TOP81
Note 2
Note 2
P101/TCUD0/TICC01
Note 2
P102/TIUD0/TO1
User's Manual U16580EE3V1UD00
Delay Noise Elimination
Type Time
Analog Several 10 ns
Delay (typ.)
Digital 4 to 5 clocks
delay
Analog 60 ns to 200 ns
Delay
Digital 4 to 5 clocks
delay
Sampling Clock
f /16 (250 ns @
XX
f = 64 MHz)
XX
f /64 (1 µs @
XX
f = 64 MHz)
XX
f /16 (250 ns @
XX
f = 64 MHz)
XX
f /64 (1 µs @
XX
f = 64 MHz)
XX
965