NEC V850E/PH2 User Manual page 405

Figure 10-48: Basic Operation Flow in PWM Mode (2/2)
(b) When values of TRnCCR0 to TRnCCR5 registers are rewritten during timer operation
Note: Regarding the sequence, the timing of <2> may differ depending on the <1> or <3> rewrite
timing, the value of the TRnCCR1 register, etc., but of <1> and <3>, always make <3> the last.
Remark: n = 0, 1
m = 0 to 5
Chapter 10 16-bit Inverter Timer/Counter R
START
Initial settings
• Clock selection
(TRnCTl0: TRnCKS2 to TRnCKS0)
•
PWM mode setting
(TRnCTl1: TRnMD3 to TRnMD0 = 0100)
Compare register setting
•
(TRnCCR0 to TRnCCR5)
Timer operation enable (TRnCE = 1)
→ Transfer of value of TRnCCRm to
TRnCCRm buffer
Upon a match between counter and
TRnCCR1 to TRnCCR5, TORn1 to
TORn5 output low level
Upon a match between
counter and TRnCCR0, counter
clear & start, and TORn1 to
TORn5 output high level.
TRnCCR0 rewrite
Upon a match between counter
and TRnCCR1 to TRnCCR5 buffers,
TORn1 to TORn5 output low level.
TRnCCR1 rewrite
• Match between TRnCCR0 buffer and
counter
• Counter clear & start
• Value of TRnCCRm is reloaded to
CCRm buffer.
User's Manual U16580EE3V1UD00
INTTRnCC1
to INTTRnCC5
occurrence
INTTRnCC0
occurrence
<1>
INTTRnCC1
to INTTRnCC5
<2>
occurrence
Note
Reload
<3>
enable
INTTRnCC0
occurrence
405