Free-Running Mode; Figure 10-50: Basic Operation Flow In Free-Running Mode - NEC V850E/PH2 User Manual

10.10.6 Free-running mode

(1) Outline of free-running mode
The operation timing of the free-running mode is shown below.
The operation for bits TRnCCS0 to TRnCCS3 of register TRnOPT0 is specified.

Figure 10-50: Basic Operation Flow in Free-Running Mode

TRnCCS1 = 0
TRnCCS0 = 0
Timer operation enable
(TRnCE = 1)
→
Transfer of values of
TRnCCR0 and
TRnCCR1 to TRnCCR0
and TRnCCR1 buffers
Match between
TRnCCR1 buffer
and counter
Match between
TRnCCR0 buffer
and counter
Counter overflow
Remarks: 1. This is an example when using the TRnCCR0 and TRnCCR1 registers. When using the
TRnCCR2 and TRnCCR3 registers, the operation is controlled in the same manner via
bits TRnCCS3 and TRnCCS2.
2. n = 0, 1
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Chapter 10 16-bit Inverter Timer/Counter R
START
Initial settings
•
Clock selection
(TRnCTL0: TRnCKS2 to TRnCKS0)
•
Free-running mode setting
(TRnCTL1: TRnMD3 to TRnMD0 = 0101)
TRnCCS1, TRnCCS0
settings
TRnCCS1 = 0
TRnCCS0 = 0
TIRn0 edge detection
settings
(TRnIS1, TRnIS0)
Timer operation enable
(TRnCE = 1)
→
Transfer of value of
TRnCCR1 to TRnCCR1
buffer
Match between
TRnCCR1 buffer
and counter
TIRn0 edge
detection, capture
of counter value
to TRnCCR0
Counter overflow
User's Manual U16580EE3V1UD00
TRnCCS1 = 1
TRnCCS0 = 1
TIRn1 edge detection
settings
(TRnIS3, TRnIS2)
Timer operation enable
(TRnCE = 1)
→
Transfer of value of
TRnCCR0 to TRnCCR0
buffer
TIRn1 edge
detection, capture
of counter value
to TRnCCR1
Match between
TRnCCR1 buffer
and counter
Counter overflow
TRnCCS1 = 1
TRnCCS0 = 1
TIRn1 and TIRn0 edge
detection settings
(TRnIS3, TRnIS2)
Timer operation enable
(TRnCE = 1)
TIRn1 edge
detection, capture
of counter value
to TRnCCR1
TIRn0 edge
detection, capture
of counter value
to TRnCCR0
Counter overflow