Chapter 5 Memory Access Control Function (Μpd70F3187 Only); Sram, External Rom, External I/O Interface; Features - NEC V850E/PH2 User Manual

Chapter 5 Memory Access Control Function (μPD70F3187 only)

5.1 SRAM, External ROM, External I/O Interface

5.1.1 Features

• SRAM is accessed in a minimum of 2 states.
• Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1
registers.
• Data wait can be controlled via WAIT pin input.
• An idle state can be inserted after a read/write cycle by setting the BCC and DVC registers.
• An address setup wait state and an address hold state can be inserted by setting the ASC register.
The memory access control function is not available on μPD70F3447.
Remark:
User's Manual U16580EE3V1UD00 181