NEC V850E/PH2 User Manual page 968

Figure 20-82: Noise Elimination Control Register (NRC) (2/2)
NRC2
0
1
NRC1
0
1
NRC0
0
1
Note: Pin group 1:
(on μPD70F31187) P03/INTP2/ADTRG0, P04/INTP3/ADTRG1, P30/RXDC0/INTP4,
(on μPD70F3447)
Pin group 2:
(on μPD70F31187) P100/TCLR0/TICC00/TOP81, P101/TCUD0/TICC01, P102/TIUD0/TO1,
(on μPD70F3447)
Cautions: 1. If the input pulse lasts for the duration of 4 to 5 clocks, it is undefined whether the
pulse is detected as a valid edge or eliminated as noise. So that the pulse is
actually detected as a valid edge, the same pulse level must be input for the
duration of 5 clocks or more.
2. If noise is generated in synchronization with the sampling clock, eliminate the
noise by attaching a filter to the input pin.
3. Noise is not eliminated if the corresponding pin is used as normal input port pin.
968
Chapter 20 Port Functions
Noise elimination clock setting for pin group 2
f /16 (250 ns @ f = 64 MHz)
XX XX
f /64 (1 µs @ f = 64 MHz)
XX XX
Noise elimination clock setting for pin group 1
f /16 (250 ns @ f = 64 MHz)
XX XX
f /64 (1 µs @ f = 64 MHz)
XX XX
Noise elimination clock setting for P00/NMI pin
f /16 (250 ns @ f = 64 MHz)
XX XX
f /64 (1 µs @ f = 64 MHz)
XX XX
P32/RXDC1/INTP5, P83/SCS300/INTP6, P84/SCS301/INTP7,
P85/SCS302/INTP8, P93/SCS310/INTP9, P94/SCS310/INTP10,
P95/SCS310/INTP11
P03/INTP2/ADTRG0, P04/INTP3/ADTRG1, P30/RXDC0/INTP4,
P32/RXDC1/INTP5, P83/SCS300/INTP6, P84/SCS301/INTP7,
P85/SCS302/INTP8, P93/INTP9, P94/INTP10,P95/INTP11
P70/TIT00/TEVTT1/TOT00, P71/TIT01/TTRGT1/TOT01,
P72/TECRT0/INTP12, P73/TIT10/TTRGT0/TOT10,
P74/TIT11/TEVTT0/TOT11, P75/TECRT1/AFO
P70/TIT00/TEVTT1/TOT00, P71/TIT01/TTRGT1/TOT01,
P72/TECRT0/INTP12, P73/TIT10/TTRGT0/TOT10,
P74/TIT11/TEVTT0/TOT11, P75/TECRT1/AFO
User's Manual U16580EE3V1UD00
Note
Note