NEC V850E/PH2 User Manual page 453

(g) Dead time settings
The dead time settings are performed with the TRnDTC0 and TRnDTC1 registers. The dead time
can be obtained with count clock cycle × TRnDTC0,TRnDTC1. The time until TORn2, TORn4,
TORn6 pin inactive change → TORn1, TORn3, TORn5 pin active change can be set with the
TRnDTC0 register. The time until TORn1,TORn3,TORn5 pin inactive change → TORn2, TORn4,
TORn6 pin active change can be set with the TRnDTC1 register.
(h) PWM cycle, duty (PWM width) setting
The duty is set with the TRnCCR1 to TRnCCR3 registers. The setting range of the TRnCCR1 to
TRnCCR3 registers is
0000H ≤ TRnCCRm ≤ (TRnCCR0 + TRnDTC0)
The TRnCCR0 and TRnDTC0 registers must be set so as to satisfy TRnCCR0 + TRnDTC0 <
FFFFH.
Remark: n = 0, 1
m = 1 to 3
(4) Operation in PWM mode with dead time
The figure shows the timing chart when TRnCCR0 = 0007H, TRnDTC0 = 0002H,
TRnDTC1 = 0002H, and the TRnCCR0 register is set to 0000H to 0007H (one part).
When the compare value of the TRnCCR1 register is incremented/decremented by 1 at a time, the
PWM width is incremented/decremented 1 count clock at a time, but at the points indicated by
arrows in the figure, incrementing/decrementing is done by TRnDTC1+1 count clock. This occurs
when the TRnCCR1 register is rewritten from the setting value of the TRnDTC0 register to
TRnDTC0+0001H (because dead time control is required).
Chapter 10 16-bit Inverter Timer/Counter R
User's Manual U16580EE3V1UD00 453