Idle State Insertion Function - NEC V850E/PH2 User Manual

Chapter 4 Bus Control Function (μPD70F3187 only)

4.7 Idle State Insertion Function

To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the
current bus cycle after the T2 state to meet the data output float delay time (tdf) on memory read
access for each CS space. The bus cycle following the T2 state starts after the idle state is inserted.
An idle state is inserted after read/write cycles for SRAM, external I/O, or external ROM.
In the following cases, an idle state is inserted in the timing.
• after read/write cycles for SRAM, external I/O, or external ROM
The idle state insertion setting can be specified by program using the bus cycle control register (BCC)
and the bus clock dividing control register (DVC).
Immediately after the system reset, idle state insertion is automatically programmed for all memory
blocks on read access.
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