Control Registers; Figure 12-7: Timer Unit Mode Register 10 (Tum10) - NEC V850E/PH2 User Manual

Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)

12.4 Control Registers

(1) Timer unit mode register 10 (TUM10)
The TUM10 register is an 8-bit register used to specify the TMENC10 operation mode or to control
the operation of the PWM output pin.
This register can be read/written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Cautions: 1. Changing the value of the TUM10 register during TMENC10 operation (TM1CE bit
of TMC register = 1) is prohibited.
2. When the CMD bit = 0 (general-purpose timer mode), setting MSEL bit = 1 (UDC
mode B) is prohibited.
After reset: 00H
7
TUM10 CMD
CMD
0
1
TOE
0
1
When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of
the TOE bit. At this time, timer output consists of the inverted phase level of the level set by
the ALVT1 bit.
ALVT1
0
1
When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of
the TOE bit. At this time, timer output consists of the inverted phase level of the level set by
the ALVT1 bit.
MSEL
0
1
When UDC mode B is set, the ENMD, CLR1, and CLR0 bits of the TMC10 register
become invalid.

Figure 12-7: Timer Unit Mode Register 10 (TUM10)

R/W Address:
6 5
0 0
TMENC10 Operation Mode Specification
General-purpose timer mode (up count)
UDC mode (up/down count)
Timer output disabled
Timer output enabled
Active Level Specification for Timer Output (TO1)
Active level is high level
Active level is low level
Mode Selection in UDC Mode (Up/Down Count)
UDC mode A.
TMENC10 can be cleared by setting the CLR1, CLR0 bits of the TMC10
register.
UDC mode B. TMENC10 is cleared in the following cases.
• Upon match with CM100 during TMENC10 up count operation
• Upon match with CM101 during TMENC10 down count operation
User's Manual U16580EE3V1UD00
FFFFF6BBH
4 3
0 TOE ALVT1
Timer Output (TO1) Control
2 1 0
0 MSEL
545