Continuous Mode (Master Mode, Transmission/Reception Mode); Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode) - NEC V850E/PH2 User Manual

16.4.4 Continuous mode (master mode, transmission/reception mode)

Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode)

Transfer Data Length = 8 Bits (CSnCL3 to CBnCL0 Bits of CBnCTL2 Register = 0000B)
CBnTX
register
SCKBn pin
SOBn pin
SIBn pin
INTCBnT
signal
INTCBnR
signal
Shift
register n
SO latch
<1>
<2>
<3>
<1> Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
<2> Set the CBnTXE and CBnRXE bits of the CBnCTL0 register to 1 at the same time as specifying
the transfer mode using the CBnDIR bit of the CBnCTL0 register, to set the transmission/
reception enabled status.
<3> Set the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply.
<4> Write transfer data to the CBnTX register (transmission start).
<5> The transmission enable interrupt (INTCBnT) is received and transfer data is written to the
CBnTX register.
<6> The reception complete interrupt (INTCBnR) is output, notifying the CPU that reading the CBnRX
(CBnRXL) register is possible.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is
cleared to 0.
<7> Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit to 0 to stop
clock supply to CSIB (end of transmission/reception).
To continue transfer, repeat steps <4> to <6> before <7>.
μPD70F3187: n = 0, 1
Remark:
μPD70F3447: n = 0
658
Chapter 16 Clocked Serial Interface B (CSIB)
MSB First (CBnDIR Bit of CBnCTL0 Register = 0),
CBnCKP Bit of the CBnCTL1 Register = 1,
CBnDAP Bit of the CBnCTL1 Register = 0,
55H
0 1 0 1 0
1 1 0 0 1
<4> <5>
User's Manual U16580EE3V1UD00
AAH
1 0 1 1 0 1
1 0 0 1 0 0
CCH
CCH
<6>
0 1 0 1 0
1 0 1 1 0
96H 00H
96H 00H
<6> <7>