Cpu Register Set; Figure 3-1: Cpu Register Set - NEC V850E/PH2 User Manual

3.2 CPU Register Set

The CPU registers of the V850E/PH2 can be classified into three categories: a general-purpose pro-
gram register set, a dedicated system register set and a dedicated floating point arithmetic register set.
All the registers have 32-bit width.
In addition, the V850E/PH2 contains special system control registers that should be initialized before
CPU operation, and a specific register controlling its clock.
For detailed description of V850E1 core, refer to V850E1 Core Architecture Manual and the
addendum for floating point arithmetic.
(1) Program register set
31
r0 (Zero register)
r1 (Assembler-reserved register)
r2
r3 (Stack pointer (SP))
r4 (Global pointer (GP))
r5 (Text pointer (TP))
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30 (Element pointer (EP))
r31 (Link pointer (LP))
31
PC (Program counter)
86
Chapter 3 CPU Functions

Figure 3-1: CPU Register Set

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User's Manual U16580EE3V1UD00
(2) System register set
31
EIPC (Status saving register during interrupt)
(Status saving register during interrupt)
EIPSW
FEPC (Status saving register during NMI)
FEPSW (Status saving register during NMI)
ECR (Interrrupt source register)
PSW (Program status word)
CTPC (Status saving register during CALLT execution)
CTPSW (Status saving register during CALLT execution)
DBPC (Status saving register during exception/debug trap)
DBPSW (Status saving register during exception/debug trap)
CTBP (CALLT base pointer)
(3) Floating point arithmetic register set
31
EFG (Flag register)
ECT (Control register)
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