10.7.2 Operation examples when peak interrupts and valley interrupts occur alternately
(1)
Register settings
Set both TRnOPT1 register bit TRnICE and TRnOPT1 register bit TRnIOE to 1.
(2)
Operation example
Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2)
(a) when TRnCMS = 0, TRnRDE = 1 (Reload Thinning Out Control) (Recommended Settings)
Counter
INTTRnCD
INTTRnOD
TRnIDS4 to 0
TRnID4 to 0
Interrupt thinning
00
out counter
* Reload is executed at the thinned out interrupt output timing. All other reload timings are ignored.
(b) when TRnCMS = 0, TRnRDE = 0 (No Reload Control)
Counter
INTTRnCD
INTTRnOD
TRnIDS4 to 0
TRnID4 to 0
Interrupt thinning
00
out counter
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Chapter 10 16-bit Inverter Timer/Counter R
02
02
04
00
01
02
01
02
02
02
Clear
01
02
00
01
00
* Reload is executed at the reload timing after rewrite.
User's Manual U16580EE3V1UD00
Reloa d*
Clear
00
01
02
03
04
04
Relo ad *
04
01
02
03
04
04
00
01
02
03
00
01
02
03
04
04
00