Cautions - NEC V850E/PH2 User Manual

17.7 Cautions

The following points must be observed when using CSI3n.
Cautions: 1. The CSI3n unit is reset and CSI3n is stopped when the CSICAEn bit of the CSIM3n
register is cleared to 0. To operate CSI3n, first set the CSICAEn bit to 1. Usually,
before clearing the CSICAEn bit to 0, clear both the CTXEn and CRXEn bits to 0
(after the end of transfer).
2. Be sure to write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn
pointers to 0 before enabling transfer by setting the CTXEn or CRXEn bit of the
CSIM3n register to 1. If the CTXEn or CRXEn bit is set to 1 without
clearing the pointers, and if the previously transferred data remains in the
CSIBUFn register, transferring that data is immediately started.
If transfer data is set to the CSIBUFn register before transfer is enabled, transfer
is started as soon as the CTXEn or CRXEn bit is set to 1.
3. If the SFA3n register is read immediately after data has been written to the
SFDB3n and SFDB3nL registers, the SFFULn, SFEMPn, and SFPn3 to SFPn0 bits
of the SFA3n register may not change their values in time.
If the SFA3n register is read before the SFFULn bit is set to 1 and a 17th data is
written, the CSIBUFn overflow interrupt (INTC3nOVF) occurs.
4. When using CSI3n in configuration with DMA transfer, observe that only single
mode is permitted (TRMDn bit of CSIM3n register = 0), and chip select CSI regis-
ters (SFCS3n, SFCS3nL) are not supported.
μPD70F3187:
Remark:
μPD70F3447:
738
Chapter 17 Clocked Serial Interface 3 (CSI3)
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00