Figure 7-6: Maskable Interrupt Processing - NEC V850E/PH2 User Manual

INTC accepted
CPU processing
Note: For the ISPR register, see 7.3.6 "In-service priority register (ISPR)" on page 242.
An INT input masked by the interrupt controllers and an INT input that occurs while another interrupt is
being processed (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt
controller. In such case, if the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by
the RETI and LDSR instructions, input of the pending INT starts the new maskable interrupt
processing.
230
Chapter 7 Interrupt/Exception Processing Function

Figure 7-6: Maskable Interrupt Processing

INT input
xxIF = 1
xxMK = 0
Priority higher than
that of interrupt currently
being processed?
Priority higher
than that of other interrupt
request?
Highest default
priority of interrupt requests
with the same priority?
Maskable interrupt request
PSW.NP
PSW.ID
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
Corresponding
Note
bit of ISPR
PC
Interrupt processing
User's Manual U16580EE3V1UD00
No
Yes
No
Is the interrupt
mask released?
Yes
No
Yes
No
Yes
No
Yes
Interrupt request held pending
1
0
1
0
restored PC
Interrupt request held pending
PSW
exception code
0
1
1
handler address