Figure 6-9: Operation Of Dma Channel 0/1 - NEC V850E/PH2 User Manual

Note: DMA transfer completion interrupt has the same interrupt vector address as the corresponding
A/D conversion completion interrupt (INTADn), and replaces that interrupt.
Remark: n = 0, 1
x = n
202
Chapter 6 DMA Functions (DMA Controller)

Figure 6-9: Operation of DMA Channel 0/1

Operation of DMA channel 0/1
no
DEx bit newly
written ?
yes
no
DEx bit = 1 ?
yes
ADDMARQn
occured ?
yes
Transfer content from ADDMAn register to
iRAM : (MARx)
Increment source pointer:
←
MARx
Decrement DMA transfer count register:
←
DTCRx
DTCRx = 0?
yes
Set DMA transfer status bit: DMASx = 1
Generate interrupt signal (INTDMAx
(number of ADC channel)
(number of DMA transfer channel)
User's Manual U16580EE3V1UD00
DMA transfer will be enabled
by write access to the
corresponding DEn bit.
no
←
ADDMAn
MARx + 2
DTCRx - 1
no
Note
)