Figure 9-32: Basic Operation Timing In Free-Running Mode (Tpnccs1 = 0, Tpnccs0 = 1) - NEC V850E/PH2 User Manual

(4) TPnCCS1 = 0, TPnCCS0 = 1 settings
When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH and free-running
count-up operation continues until TPnCE = 0 is set. The TPnCCR1 register is used as a compare
register. An interrupt signal is output upon a match between the value of the 16-bit counter and the
setting value of the TPnCCR1 register as an interval function. When TPnOE1 = 1 is set, TOPn1
performs toggle output upon mach between the value of the 16-bit counter and the setting value of
the TPnCCR1 register.

Figure 9-32: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1)

TPnCE = 1
FFFFH
16-bit counter
TIPn0
TPnCCR0
INTTPnCC0
capture interrupt
TPnCCR1
CCR1 buffer
0000H
register
INTTPnCC1
Remarks: 1. D , D
00
D , D
10
2. TIPn0: Set to falling edge detection (TPnIS1, TPnIS0 = 10B)
3. n = 0 to 7
(5) Overflow flag
When the counter overflows from FFFFH to 0000H in the free-running mode, the overflow flag
(TPnOVF) is set to 1 and an overflow interrupt (INTTPnOV) is output.
Be sure to confirm that the overflow flag (TPnOVF) is set to "1" when the overflow interrupt
(INTTPnOV) has occurred.
The overflow flag is cleared by writing 0 from the CPU.
Chapter 9 16-Bit Timer/Event Counter P
D
D
10
0000H
D
10
D
10
, D , D : Values captured to TPnCCR0 register (0000H to FFFFH)
01 02 03
, D : Setting value of TPnCCR1 register (0000H to FFFFH)
11 12
User's Manual U16580EE3V1UD00
00
D
01
D
11
D D
00
D
11
D
11
D
02
D
12
D
11
D
01 02
D
03
D
03
D
12
D
12
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